1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, more particularly to a method for forming intermetal dielectric of semiconductor device for reducing chemical mechanical polishing process time.
2. Description of the Related Art
An intermetal dielectric is a film sandwiched between a lower metal wiring and an upper metal wiring. A surface planarization in the intermetal dielectric is required so as to ensure photo margin and to minimize wiring length in semiconductor manufacturing process. In order to obtain a surface-planarized intermetal dielectric, those conventional methods of using reflow, spin-coating or chemical mechanical polishing (hereinafter "CMP") have been performed.
According to the method using reflow, a layer having liquidity as an intermetal dielectric, for example, a Boron Phosphor Silicate Glass (hereinafter "BPSG") layer, is deposited on an insulating layer on which a metal wiring has been previously formed, and then, the BPSG layer is reflowed by heat-treating thereby obtaining the surface planarization in the intermetal dielectric.
According to the method using spin coating, with rotating a wafer, an insulating material in the glass state is sprayed to a wafer on which a metal wiring has been previously formed. And then, the insulating material in the glass state is cured thereby obtaining an intermetal dielectric and simultaneously obtaining the surface planarization thereof. Herein, a layer given by the spin coating method is called an SOG (spin on glass) layer.
According to the method using CMP process, a chemical solution, i.e. a slurry is sprayed to an intermetal dielectric which is previously formed and simultaneously the intermetal dielectric is polished by a polisher. Therefore, the surface planarization of the intermetal dielectric is obtained according to a chemical reaction between the slurry and the intermetal dielectric and a mechanical polishing by the polisher. The method using the CMP process is a leading method applicable to the next generation devices since this method enables the global planarization and the planarization under low temperature that can not be obtained by the method using reflow.
FIG. 1 is a cross-sectional view for showing an intermetal dielectric which is formed according to a conventional technology. As shown in FIG. 1, a first insulating layer 10 is formed on a semiconductor substrate (not shown) having device such as transistors (not shown) therein. Metal wirings 20 in which a Ti/TiN layer 12, an Al layer 14 and a TiN layer 16 are stacked successively, are formed on the first insulating layer 10. The second insulating layer 22 is formed on the metal wirings 20 and the first insulating layer 10 so that the second insulating layer covers the metal wirings 20, and the third insulating layer 24 is formed on the second insulating layer 22. Herein, an intermetal dielectric 30 consists of a second insulating layer 22 and a third insulating layer 24.
FIG. 2 is a cross-sectional view for showing a result that the CMP process is performed at the intermetal dielectric of FIG. 1. As shown in FIG. 2, the third insulating layer 24 is planarized according to the CMP process. However, a complete planarization at the third insulating layer 24 is not obtained since dishing D is occurred at the region between metal wirings 20, The dishing D is originated from the step difference occurred at the third insulating layer 24.
Generally, the dishing D is influenced by the pattern density of bottom layers and by the step difference. That means, the size of dishing is small in a region having short distance between patterns and low step difference while the size of the dishing is large in a region having long distance between patterns and high step difference. FIG. 3 shows a region to be polished according to the CMP process. As shown in FIG. 3, the hatched region A should be polished so as to obtain the surface planarization in the intermetal dielectric 40 according to the CMP process. In order to polish the hatched region A completely, CMP process time is increased and the dishing D is occurred during the CMP process.
Accordingly, in FIG. 1, since the third insulating layer 24 has a high step difference copied thereto, the CMP process time is increased. Furthermore, although the third insulating layer 24 is planarized by the CMP process, the dishing D is occurred between the metal wirings 20. Additional CMP processes should be performed so as to eliminate the dishing D, time for planarization in the intermetal dielectric 30 is increased.